1. Field of the Invention
The present invention relates to a semiconductor device having a fine gate structure and a method of making the same.
2. Description of the Related Art
Recently, with fine pattern structures of integrated circuits, it has been required that gate electrodes of MOSFETs have the fine structure. For example, although variations in gate structures are caused by lithography and anisotropic etching processes, it can not be neglected that electrical characteristics of MOSFETs are affected by the variations.
FIGS. 6A to 6D are sectional views showing process steps of making a conventional MOSFET.
As shown in FIG. 6A, a field oxide film 2 is formed on a surface of a silicon substrate 1 by a selective oxidation process. Thereafter, a gate oxide film 3 with a thickness of about 10 nm is formed on an element region 1a, surrounded by the field oxide film 2, of the surface of the silicon substrate 1 by a thermal oxidation process.
As shown in FIG. 6B, a polysilicon layer 4 with a thickness of approximately 200 nm is deposited over the gate oxide film 3 and the field oxide film 2 by a CVD process. P (phosphorus) is introduced into the polysilicon layer 4 by diffusion or ion implantation techniques. A resist pattern 5 is then formed on the polysilicon layer 4 by photolithographic techniques.
As shown in FIG. 6C, the polysilicon layer 4 and the gate oxide film 3 are anisotropically etched away, using the resist pattern 5 as a mask. Subsequently, ion implantation is performed by using the resist pattern 5 and the field oxide film 2 as masks, forming source and drain regions 6 in the silicon substrate 1 by self-alignment. Thereafter, the resist pattern 5 is removed to provide a gate electrode 7 on the gate oxide film 3.
As shown in FIG. 6D, an SiO.sub.2 film 8 of about 300 nm in thickness is deposited over the substrate surface by the CVD process. First and second contact holes 8a and 8b are formed in the SiO.sub.2 film 8, and a third contact hole (not shown) is also formed by the photolithographic and anisotropic etching processes. The third contact hole is formed in the field oxide film (not shown). Aluminum wiring layers 9 are connected to the source and drain regions 6 through the contact holes 8a and 8b. The aluminum wiring layer 9 (not shown) is also connected to the gate electrode 7 through the third contact hole.
In the structure, the resist pattern 5 shown in FIG. 6B is formed by the photolithographic technique. In this case, a variation in length l.sub.1 of the resist pattern 5 results from the dimensional variation caused by the photolithographic technique, and the value of the variation becomes about 0.05 .mu.m. Therefore, when the gate electrode 7 having the gate length of 0.5 .mu.m is formed, the variation in the gate length caused by the resist pattern 5 reaches 10%.
The gate electrode 7 is formed by the anisotropic etching using the resist pattern 5 as the mask. The anisotropic etching also produces a dimensional variation, leading to a further variation in the gate length. The value of this variation is approximately equal to that of the variation caused by the photolithography.
As a result, when the gate electrode 7 having the gate length 2 of 0.5 .mu.m shown in FIG. 6C, the variation in the gate length reaches about 20% owing to the dimensional variations caused by the photolithography and the anisotropic etching, respectively.
In formation of the gate electrode having the gate length of shorter than 0.35 .mu.m, therefore, the variations resulting from the photolithography and the anisotropic etching are no longer negligible.
Further, it may be considered that a length of the gate electrode in the direction of gate width is decreased to obtain a fine gate electrode. FIG. 7 is a plan view showing a pattern of the MOSFET illustrated in FIG. 6D. Referring to FIG. 7, a length y.sub.3 of the gate electrode 7 in the direction of gate width is the sum of a length y.sub.1 required for a gate fringe, a length y.sub.2 required to provide the third contact hole 8c for connecting the wiring layer to the gate electrode 7, and a gate width w. Therefore, in order to reduce the length y.sub.3 of the gate electrode 7 in the gate width direction, it may be considered to eliminate the length y.sub.2 required for providing the wiring layer.
The third contact hole 8c is formed in the field oxide film in the above conventional MOSFET, but it must be formed in the element region in order to eliminate the length y.sub.2. When the contact hole 8c is formed in the element region, however, the gate oxide film may be destroyed by a damage caused by etching it during formation of the contact hole 8c.